Signals in integrated circuits are generally propagated along interconnect lines (e.g., electrically conductive features, such as, wires, traces and the like) that couple various transistors and other circuit components together. In some cases, these lines can be relatively long and can introduce delays, noise, and signal degradation. Usually, the longer the line, the longer the delay and the more prone to noise and degradation the signal can be. The delay, noise, and signal degradation, however, can be reduced by splitting the line into segments and inserting buffers (e.g. repeaters) to help drive the signal along the line. These buffers may in some embodiments include one or more inverters, each formed, for example, with a p-channel field effect transistor (pFET) with its source coupled to a supply voltage node, such as VCC, and its drain coupled to the drain of an n-channel field effect transistor (nFET). The source of the nFET may be coupled to a reference voltage node, such as ground. As an input signal applied to the gates of the nFET and pFET changes (e.g., as a signal propagates through the inverter(s)), the output signal may transition (e.g., switch) between logical high (‘1’) and logical low (‘0’) values. The signals may be data signals, clock signals, or any other type of signal.
The frequency at which a device can be operated depends in part on various delays to the signals as they propagate along (e.g. pass through) the lines of an integrated circuit. The delays may include transition delays (i.e., the delay incurred when the signal transitions from a logical high to a logical low, or vice versa), propagation delays between different sequential or combinational circuits, and so forth. Generally, the shorter the delays, the faster the frequency at which the device can be operated. In other words, as the operating frequency of a device increases, signal delays generally must become shorter.
Devices with Dual Data Rate (DDR) lines transfer data on both the rising and falling edges of a clock signal, thereby doubling the effective bandwidth or throughput of the line as compared to a non-DDR device. However, because both edges of a clock signal contain information, the timing of the signals generally should be more precise. For example, the rising edge of a clock or data signal may need to be shaped substantially similar to the falling edge of the signal in order to ensure that the signal transitions meet a certain specification or to ensure that data is available as required.
Drive strength is the relative ability of a circuit, such as a buffer, to source or sink current during the transition of logical states of a propagating signal. Drive strength is often characterized separately for different FETs in a circuit, such as the pull-up pFET of an inverter and the pull-down nFET of the inverter. Taking an inverter as an example, the rate at which it can transition its output node from a logical high to a logical low voltage level depends in part on the drive strength of the pull-down nFET. Specifically, the drive strength of the pull-down nFET influences the rate that the inverter will be able to discharge the output node to a reference voltage node, such as ground. The rate at which the inverter can transition its output node from a logical low to a logical high voltage level depends in part on the drive strength of the pull-up pFET in the circuit. Specifically, the drive strength of the pull-up pFET influences how fast or how slow the circuit will be able to charge the output node from a supply voltage node, such as VCC, a pumped voltage Vccp, or a voltage stepped down from Vcc. The drive strength of the pull-up and pull-down FETs is inversely related to the delay incurred during signal transitions because the greater the drive strength of the FETs, the faster the inverter or other circuit will be able to change the voltage on its output node.
The shape of the output signal at the output node is determined by the pull-up and pull-down rates. Specifically, the shape of the output signal falling from high-to-low is determined by the pull-down rate, while the shape of the output signal rising from low-to-high is determined by the pull-up rate.
The drive strength of a FET may be a function of, among other things, the geometry of the FET, such as its W/L ratio and the carrier type (i.e. electrons in nFETs and holes in pFETs). Specifically, the larger the W/L ratio, the greater the drive strength. Also, for the same geometry, nFETs typically have greater drive strengths than pFETs due to the higher relative mobility of the electron carriers in nFETs as compared with the hole carriers in pFETs.
In order to have substantially symmetric high-to-low and low-to-high output signal shapes for an inverter, the drive strength of the pull-up pFET may need to be substantially equal to the drive strength of the pull-down nFET. For example, substantially equal drive strengths may be drive strengths of the pull-up and pull-down transistors provide transitions from low-to-high takes approximately the same time as transitions from high-to-low. In some embodiments, substantially equal may mean within +/−10% of one another. Substantially symmetric may mean rise time and fall time are within +/−10%. As the load capacitance seen at the output node does not usually change, the load will be able to charge during a low-to-high transition at the same rate as the load discharges during a high-to-low transition if the respective nFET and pFET have similar drive strength (e.g. current capabilities). For other circuits, the drive strength of the pull-up circuit may need to be substantially equal to the drive strength of the pull-down circuit in order to similarly have substantially symmetric high-to-low and low-to-high output signal shapes.
Taking an inverter again as an example, circuit designers typically try to equate the drive strength of its pFET with the drive strength of its nFET by altering the geometries of one of the FETs. For example, if the nFET has a minimum channel length and width, the pFET is designed with a width that is some factor (e.g. 2.5×) larger than the nFET to compensate for the holes of the pFET having a lower mobility and/or to compensate for differing levels of doping. The factor is processing technology dependent, and is usually obtained by taking the difference in hole and electron mobility and extrapolating how much wider a pFET needs to be to drive the same amount of current as an nFET.
However, despite attempts to equate the drive strength of an nFET and a pFET in, for example, an inverter, by widening the channel of the pFET, the actual drive strengths of the nFET and pFET in operation may differ. The difference may be, for example, due to temperature variations, doping or other manufacturing variations, and so forth. As discussed above, this difference in drive strength may lead to output signals that are not symmetrically shaped for the high-to-low and the low-to-high transitions, thus potentially leading to unanticipated or undesirable delay differences in signal propagation.